1. Field of the Invention
The present invention is generally related to an one-chip microcomputer capable of internally producing ECC data to add the ECC data to user data. More specifically, the present invention is directed to such an one-chip microcomputer capable of reducing a work load of a user, and also capable of reducing a memory capacity without increasing EEPROM write time based upon the ECC data.
2. Description of the Related Art
EEPROMs (electrically erasable programmable read-only memories) are such memories capable of erasing and/or writing data (including flash EEPROMs), and are usually employed in one-chip microcomputers and the like capable of storing programs. To increase reliability of data saved in EEPROMs, the following error correction method is effectively utilized. That is, while ECC (error correction code) data is added to user data and then the resulting user data added with the ECC data is stored, the error correction is carried out by using the ECC data with respect to the read user data. Conventionally, such an ECC data adding operation is carried out in such a manner that while the ECC data is produced from the user data by using the dedicated software, the produced ECC data is stored into the EEPROM in combination with the user data.
For example, a one-chip microcomputer used to control an engine of an automobile executes such an important control, for example, an engine revolution number control and a fuel injection control based upon a control program. In the case that a storage content of a ROM (read-only memory) for previously storing this control program is changed, this one-chip microcomputer executes an abnormal process operation, resulting in a dangerous condition. As a consequence, when a user stores use data (program and the like) into the ROM, the ECC data is additionally stored in this ROM. When the one-chip microcomputer reads out the user data, if one bit error occurs, then this one-chip microcomputer may correct this 1 bit error, and also if more than 2-bit error occurs, then this one-chip microcomputer may indicate xe2x80x9cabnormalxe2x80x9d conditions.
Furthermore, when a bug is found in user data (computer program) previously stored in a ROM, an automobile manufacturer should recall sold automobiles so as to replace the defective one-chip microcomputers by properly set one-chip microcomputers. In the bug case, this automobile manufacturer is required to replace an engine control assembly containing a defective one-chip microcomputer when a ROM is arranged by a rewritable ROM such as a mask ROM. In this rewritable ROM case, not only the cost of this engine control assembly, but also the replacement cost are necessarily required. As a result, this automobile manufacturer should accept a large amount of loss. Under such a circumstance, if a ROM of a one-chip microcomputer is arranged by an EEPROM, then the automobile manufacturer is merely required to rewrite a program saved in this EEPROM via a connector of this one-chip microcomputer, so that a total cost of solving the bug problem can be reduced.
FIG. 20 is an explanatory diagram for explaining one conventional ECC data producing/adding method executed in an EEPROM. Now, this conventional ECC data producing/adding method will be explained with reference to FIG. 20.
First, a user forms a predetermined program (step 101 of FIG. 20(a)) so as to produce ECC data. It is now assumed that as user data 102, data defined from 00000H up to 0FFFFH are inputted. The user produces the ECC data based the user data 102 by employing exclusively-used software in accordance with the formed program (step 103 in FIG. 20(a)). As a result, data defined from 10000H up to 14FFFH are produced as the ECC data 104. Next, the ECC data 104 is added to the user data 102 so as to produce data defined from 00000H up to 14FFFH as write data 105, and then these produced write data are written into an EEPROM built in a microcomputer (not shown) (step 106 in FIG. 20(a)). In this case, the write data 105 are written by way of an exclusively-used data writer, or an on-board writing manner.
FIG. 20(b) illustrates an address map on the EEPROM. In this address map, addresses from 00000H to 0FFFFH are allocated as the user data, and also addresses from 10000H to 14FFFH are allocated as the ECC data. A volume of ECC data requires 5 bits in the case of 16-bit data. As a result, a data region as shown in FIG. 20(b) is required.
However, in the above-described conventional ECC data producing/adding method, since the ECC data is produced and the user data is separately processed, there is a problem that the exclusively used software capable of producing the ECC data based upon the user data is required.
Also, since the ECC data is mapped at the addresses after the user data, the data defined from 10000H up to 14FFFH are written as the ECC data in addition to the user data defined from 00000H up to 0FFFFH. As a result, there is another problem that the data writing time would be increased by approximately 30 percents.
Furthermore, since the entire data amount of write data is increased by approximately 30 percents because of the employment of these ECC data, there is a further problem that the total memory capacity of the external memory of the entire system must be increased by approximately 30 percents.
On the other hand, conventionally, one conventional technical idea has been proposed such that the ECC data producing circuit constituted by employing the logic circuits is built in the one-chip microcomputer. Very recently, bitwidths of data buses employed in one-chip microcomputers are increased more and more. That is, although the conventional data buses own bitwidths of 8 bits, the current data buses own bitwidth of 32 bits, or 64 bits. Under such a wide bitwidth trend condition, when a ECC data producing circuit is arranged by logic circuits, an entire circuit scale would be increased in an exponential manner in connection with a increase of such a bitwidth of a data bus. Therefore, an area occupied by this ECC data producing circuit with respect to a semiconductor chip would be necessarily increased.
In the case that an EEPROM is employed so as to store thereinto a program used in an one-chip microcomputer, a ECC data producing circuit is used only when this computer program is stored, but not used when this computer program is executed. Nevertheless, such a technical idea that the ECC data producing circuit having the large circuit scale is built in the one-chip microprocessor would cause the cost effective performance characteristic of this one-chip microcomputer to be deteriorated.
In view of the above-described problems, it is an object of the present invention to provide a one-chip microcomputer capable of internally producing ECC data.
It is another object of the present invention to provide a one-chip microcomputer capable of reducing a workload given to a user, and further capable of reducing a necessary capacity of a memory without increasing ECC data writing time of an EEPROM.
According to a first aspect of the present invention, there is provided a microcomputer comprising:
an electrically erasable memory for temporarily storing thereinto externally supplied user data and ECC (error correction code) data corresponding to the user data;
a program storage memory for previously storing thereinto a program; and
a CPU (central processing unit) for reading the program from the program storage memory so as to produce the ECC data based upon the externally supplied user data, and for sequentially correcting errors contained in the externally supplied user data by using the produced ECC data corresponding to the externally supplied user data.
In the foregoing, it is desirable that, when the externally supplied user data contains a 1-bit error, the CPU corrects the 1-bit error based on the produced ECC data read from the electrically erasable memory, whereas when the externally supplied user data contains more than 2-bit errors, the CPU indicates an abnormal condition.
Furthermore, a mode is preferable in which the electrically erasable memory is a flash memory.
According to a second aspect of the present invention, there is provided a one-chip microcomputer comprising:
an EEPROM (electrically erasable read-only memory) for temporarily storing externally-supplied user data into a user data storage region thereof and also for temporarily storing ECC (error correction code) data corresponding to the user data into an ECC data storage region thereof;
a read-only memory for previously storing thereinto a program; and
a CPU (central processing unit) for reading the program from the read-only memory so as to produce the ECC data based upon the externally supplied user data, and for sequentially correcting errors contained in the externally supplied user data by using the produced ECC data.
In the second aspect, it is preferable that, while a preselected amount of the user data are sequentially entered from an external data source, the CPU sequentially produces the ECC data from the preselected amount of user data; writes both the user data and the ECC data corresponding to the user data into the user data storage region of the EEPROM and also the ECC data storage region thereof respectively at the same addresses of the EEPROM; and reads both the user data and the ECC data from the user data/ECC data storage regions at the same addresses so as to sequentially perform the error correction.
Also, it is preferable that, while a preselected amount of the user data are sequentially entered from an external data source, the CPU sequentially produces the ECC data from the preselected amount of user data until one process cycle is completed; writes the user data and ECC data produced after one process cycle has been completed into the user data storage region of the EEPROM and an ECC data storage region thereof having an address decremented by 1 from the address of the user data storage region; and also reads both the user data and the ECC data stored at the same addresses of the EEPROM so as to sequentially perform the error correction.
Furthermore, it is desirable that, while a preselected amount of the user data are sequentially entered from an external data source, the CPU sequentially produces the ECC data from the preselected amount of user data until one process cycle is completed; writes the user data and ECC data after one process cycle has been completed into the user data storage region of the EEPROM and the ECC data storage region thereof at the same addresses, respectively; and also reads the user data stored in the user data storage region of the EEPROM and ECC data stored in the ECC data storage region thereof having an address incremented by 1 from the address of the user data storage region so as to sequentially perform the error correction.
Furthermore, it is desirable that, while a preselected amount of user data are sequentially entered from an external data source, the CPU sequentially produces the ECC data from the preselected amount of user data; outputs invalid data in the case that the production of the ECC data is not accomplished until next user data is entered; writes both the user data and valid ECC data corresponding thereto into the user data storage region of the EEPROM and the ECC data storage region thereof at the same addresses, respectively; and also reads the user data and the ECC data stored at the same addresses of the user data/ECC data storage regions of the EEPROM so as to execute the error correction.
Also, according to a third aspect of the present invention, there is a one-chip microcomputer comprising:
an EEPROM (electrically erasable programmable read-only memory) for temporarily storing thereinto both user data and ECC (error correction code) data corresponding to the user data into a user data storage region and an ECC data storage region, respectively;
storage means for previously storing thereinto a program used to produce ECC data based upon user data;
write control means for controlling writing of both the user data and the ECC data into the EEPROM; and
a CPU (central processing unit) for producing ECC data from the user data stored in the EEPROM in accordance with the program, and for storing the produced ECC data and the original user data into the ECC data storage region of the EEPROM and the user data storage region thereof under control of the write control means; and further for reading the user data stored in the user data storage region and the ECC data stored in the ECC data storage region so as to correct an error contained in the user data based upon both the read user data and the read ECC data.
In the third aspect, a mode is preferable in which:
the CPU includes an internal register into which a preselected amount of user data are sequentially stored from an external data source;
the EEPROM further includes a user data register to which the preselected amount of user data are transferred, and an ECC data register; and
the CPU produces ECC data from a predetermined amount of user data stored in the internal register thereof; transfers the produced ECC data to the ECC data register contained in the EEPROM; writes both the user data of the user data register and the ECC data of the ECC data register into the user data storage region of the EEPROM and the ECC data storage region thereof at the same addresses; and also reads both the user data and the ECC data stored at the same addresses of the EEPROM so as to perform the error correction.
Furthermore, a mode is desirable in which:
the write control means further includes a user data stack register into which a preselected amount of user data are stored from an external data source, and an ECC data stack register;
the CPU further includes an internal register into which a preselected amount of user data are stored from the external data source;
in a first process cycle, the CPU transfers user data stored at a first address to the user data register contained in the write control means, and stores the user data storage transferred to the user data register into the user data region contained in the EEPROM;
in a next process cycle and succeeding process cycles, the CPU produces ECC data from a predetermined amount of user data stored in the preceding process cycle; transfers the produced ECC data to the ECC data stack register contained in the write control means; transfers the user data to the user data stack register contained in the EEPROM and also the ECC data to the ECC data register; decrements a write address by 1 with respect to the ECC data storage region of the EEPROM; and writes both the user data stored in the user data register and the ECC data stored in the ECC data register into both the user data storage region and the ECC data storage region of the EEPROM, respectively; and also repeatedly executes the above-defined process operations thereof;
in a final process cycle, the CPU produces ECC data from a predetermined amount of user data stored in the preceding process cycle; transfers the produced ECC data to the ECC data stack register contained in the write control means; transfers the produced ECC data to the ECC data register contained in the EEPROM; decrements a write address by 1 with respect to the ECC data storage region of the EEPROM; and writes the ECC data stored in the ECC data storage region of the EEPROM;
the CPU reads both the user data and the ECC data stored at the same addresses of the EEPROM so as to sequentially execute the error corrections.
Furthermore, it is preferable that the write control means further includes a user data stack register into which a preselected amount of user data are stored from an external data source, and an ECC data stack register;
the CPU further includes an internal register into which a preselected amount of user data are stored from the external data source;
in a first process cycle, the CPU transfers user data stored at a first address to the user data register contained in the write control means, and stores the user data transferred to the user data register into the user data storage region contained in the EEPROM;
in a next process cycle and succeeding process cycles, the CPU produces ECC data from a predetermined amount of user data stored in the preceding process cycle; transfers the produced ECC data to the ECC data stack register contained in the write control means; transfers the user data to the user data stack register contained in the EEPROM and also the ECC data to the ECC data register; and writes both the user data stored in the user data register and the ECC data stored in the ECC data register into both the user data storage region and the ECC data storage region of the EEPROM, respectively; and also repeatedly executes the above-defined process operations thereof;
in a final process cycle, the CPU produces ECC data from a predetermined amount of user data stored in the preceding process cycle; transfers the produced ECC data to the ECC data stack register contained in the write control means; transfers the produced ECC data to the ECC data register contained in the EEPROM; and writes the ECC data stored in the ECC data region of the EEPROM; and also reads both user data of the EEPROM and ECC data stored at an address incremented by 1 from an address of the read user data so as to sequentially execute the error correction.
With the above-described one-chip microcomputer, the user data are externally inputted, the CPU sequentially produces the ECC data from a preselected amount of entered user data in accordance with the internal program, and thereafter both the user data and the produced ECC data corresponding thereto are stored into the user data storage region and the ECC data storage region of the EEPROM. As a consequence, the workload given to the user can be greatly reduced, as compared with the user workload in such a case that the ECC data is produced outside the one-chip microcomputer. Furthermore, since such an external memory for temporarily storing thereinto the produced ECC data is no longer required so as to produce the ECC data, the entire system cost can be lowered. In addition, since both the user data and the ECC data are written into EEPROM at the same time, the data writing time with respect to EEPROM can be reduced, as compared with the data writing time required when the ECC data is written from the external memory into this EEPROM.